Datasheet

If the RAMECC is configured in a way that requires it to be periodically serviced by the CPU through
interrupts or similar, improper operation or data loss may result during debugging.
17.5.8 Register Access Protection
All registers with write-access are optionally write-protected by the peripheral access controller (PAC),
except the following registers:
• Interrupt Flag Status and Clear (INTFLAG) register
• Status (STATUS) register.
Write-protection is denoted by the Write-Protected property in the register description.
Write-protection does not apply to accesses through an external debugger. Refer to the Peripheral
Access Controller chapter for details.
17.5.9 Analog Connections
Not applicable.
17.6 Functional Description
17.6.1 Principle of Operation
Error Correcting Code (ECC) is implemented to detect and correct errors that may arise in the RAM
arrays. The ECC logic is capable of double error detection and single error correction per 8-bit byte.
Upon single bit error detection, the Single Bit Error interrupt flag is raised (INTFLAG.SINGLEE). If a dual
error is detected, the Dual Error interrupt flag (INTFLAG.DUALE) is raised. When the first error is
detected, the ERRADDR register is frozen with the failing address and remains frozen until
INTFLAG.DUALE and INTFLAG.SINGLEE are cleared. If a dual bit error occurs while
INTFLAG.SINGLEE is set, the ERRADDR register is updated with the dual bit error information and
INTFLAG.DUALE is also set.
The INTFLAG.SINGLEE and INTFLAG.DUALE bits are both cleared on ERRADDR read.
The block diagram shows the ECC interface. When ECC is disabled (CTRLA.ECCDIS=1), the ECC field
in RAM is left unchanged on writes. On reads, ECC errors are not corrected or flagged.
Related Links
17.3 Block Diagram
17.6.2 Interrupts
The RAMECC has the following interrupt sources:
• Dual Bit Error (DUALE): Indicates that a dual bit error has been detected.
• Single Bit Error (SINGLEE): Indicates that a single bit error has been detected.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status
and Clear (INTFLAG) register is set when the interrupt condition occurs.
Each interrupt can be individually enabled by writing a '1' to the corresponding bit in the Interrupt Enable
Set (INTENSET) register, and disabled by writing a '1' to the corresponding bit in the Interrupt Enable
Clear (INTENCLR) register.
SAM D5x/E5x Family Data Sheet
RAMECC – RAM Error Correction Code (ECC)
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 205