Datasheet

17.5.2 Power Management
The RAMECC will continue to operate in any sleep mode where the selected source clock is running. The
RAMECC’s interrupts can be used to wake up the device from sleep modes. Refer to the Power Manager
chapter for details on the different sleep modes.
Related Links
18. PM – Power Manager
17.5.3 Clocks
The RAMECC bus clock is provided by the Main Clock Controller (MCLK) through the AHB-APB B bridge.
The clock is enabled and disabled by writing RAMECC bit the in the APB B Mask register
(MCLK.APBBMASK.RAMECC). See the register description for the default state of the RAMECC bus
clock.
Related Links
15.6.2.6 Peripheral Clock Masking
17.5.4 DMA
Not applicable.
17.5.5 Interrupts
The interrupt request line is connected to the interrupt controller. Using the RAMECC interrupt(s) requires
the interrupt controller to be configured first.
Related Links
10.2 Nested Vector Interrupt Controller
17.5.6 Events
Not applicable.
Related Links
31. EVSYS – Event System
17.5.7 Debug Operation
When the CPU is halted in debug mode the RAMECC will correct and log ECC errors based on the table
below.
Table 17-1. ECC Debug Operation
DBGCTRL.ECCELOG DBGCTRL.ECCDIS Description
0 0 ECC errors from debugger reads
are corrected but not logged in
INTFLAG.
1 0 ECC errors from debugger reads
are corrected and logged in
INTFLAG.
X 1 ECC errors from debugger reads
are not corrected or logged in
INTFLAG.
SAM D5x/E5x Family Data Sheet
RAMECC – RAM Error Correction Code (ECC)
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 204