Datasheet

Table Of Contents
Table 54-64. GCLK_USB Clock Setup Recommendations
Clock setup USB Device USB Host
DFLL48M Open loop No No
Close loop, Ref. internal OSC source No No
Close loop, Ref. external XOSC source Yes No
Close loop, Ref. SOF (USB recovery mode)
(1)
Yes
(2)
N/A
FDPLL internal OSC (32K, 8M…) No No
external OSC (<1MHz) Yes No
external OSC (>1MHz) Yes
(3)
Yes
Note: 
1. When using DFLL48M in USB recovery mode, the Fine Step value must be 0xA to guarantee a
USB clock at +/-0.25% before 11ms after a resume. Only usable in LDO regulator mode.
2. Very high signal quality and crystal-less. It is the best setup for USB Device mode.
3. FDPLL lock time is short when the clock frequency source is high (> 1 MHz). Thus, FDPLL and
external OSC can be stopped during USB suspend mode to reduce consumption and guarantee a
USB wake-up time (See TDRSMDN in the USB 2.0 specification).
SAM D5x/E5x Family Data Sheet
Electrical Characteristics at 85°C
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Datasheet
DS60001507E-page 2034