Datasheet

...........continued
Name Description Mode V
DD
= 1.8V V
DD
= 3.3V Units
Min. Typ. Max. Min. Typ. Max.
t
DDR_QSPI0f
Input Setup Time Master DDR mode 0
fall edge
3.87 - - 3.85 - - ns
t
DDR_QSPI1f
Input Hold Time Master DDR mode 0
fall edge
0.00 - - 0.19 - -
t
DDR_QSPI2f
Data Out Valid Time Master DDR mode 0
fall edge
- - 2.1 - - 2.03
t
DDR_QSPI0r
Input Setup Time Master DDR mode 0
rise edge
3.81 - - 3.57 - -
t
DDR_QSPI1r
Input Hold Time Master DDR mode 0
rise edge
0.06 - - 0.19 - -
t
DDR_QSPI2r
Data Out Valid Time Master DDR mode 0
rise edge
- - 3.13 - - 2.12
Note:
1. These values are based on simulation. They are not covered by production test limits or
characterization.
2. All timing characteristics are given for 20pF capacitive load.
Table 54-58. QSPI Maximum Frequency examples
(1)
QSPI
Mode
CLK_QSPI2
X _AHB
CLK_QSPI
_AHB
Max.
CPU_CLK
Max. QSPI
Speed
Conditions
SDR X 120 MHz 120 MHz 60 MHz BAUD -> BAUD[7:0]
must be greater than 0 to
ensure QSPI clock
frequency is as per
electrical specifications
provided in table 54-52.
X 75 MHz 75 MHz 75 MHz -
DDR 132 MHz 66 MHz 66 MHz 66 MHz -
Note: 1. Examples shown do not supersede the electrical specifications shown in Table 54-52. QSPI
Timing Characteristics.
SAM D5x/E5x Family Data Sheet
Electrical Characteristics at 85°C
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 2025