Datasheet

...........continued
Symbol Parameter Conditions Min. Typ. Max. Units
F
CloseJitter
Period Jitter f
REF
= XTAL, 32.768 kHz, 100 ppm
DFLLMUL = 1464
- - 0.42 ns
T
Lock
Lock time F
REF
= XTAL, 32.768 kHz, 100 ppm
DFLLMUL = 1464
DFLLVAL after Reset
DFLLCTRL.BPLCKC = 1
DFLLCTRL.QLDIS = 0
DFLLCTRL.CCDIS = 1
DFLLMUL.FSTEP = 10
- 429 1145 µs
Note:
1. These values are based on simulation. They are not covered by production test limits or
characterization.
2. To ensure that the device stays within the maximum allowed clock frequency, any reference clock
for the DFLL in close loop must be within 2% error accuracy.
Table 54-52. DFLL48M Power Consumption
Symbol Parameter Conditions Ta Min. Typ. Max. Units
I
DD
Current Consumption Open Loop mode - DFLLVAL after reset VCC =
3.3V
Max. 85°C
Typ. 25°C
- 400 854 µA
Closed Loop mode - f
REF
= 32 .768 kHz VCC =
3.3V
- 404 851 µA
54.13.5 Fractional Digital Phase Lock Loop (FDPLL) Characteristics
Table 54-53. Fractional Digital Phase Lock Loop Characteristics
(2)
Symbol Parameter Conditions Min. Typ. Max. Units
f
IN
(1)
Input Frequency 32 - 3200 kHz
f
OUT
(1)
Output Frequency 96 - 200 MHz
Jp Period jitter (Peak-Peak
value)
f
IN
= 32 kHz, f
OUT
= 96 MHz - 1.9 2.7 %
f
IN
= 32 kHz, f
OUT
= 200 MHz - 3.4 4.9
f
IN
= 3.2 MHz, f
OUT
= 96 MHz - 2.0 3.0
f
IN
= 3.2 MHz, f
OUT
= 200 MHz - 4.3 6.6
t
LOCK
Lock Time After startup, time to get lock signal. f
IN
= 3.2 MHz
- 54 95 μs
Duty
(1)
Duty cycle - - 50 - %
SAM D5x/E5x Family Data Sheet
Electrical Characteristics at 85°C
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 2018