Datasheet

Note:
1. These values are based on characterization. These values are not covered by test limits in
production.
2. All values expressed in decibel refer to the full scale input and are tested with an input signal
0.35dB below full scale; THD measured on the first seven harmonics of the input signal.
Table 54-27. Power Consumption
Symbol Parameters Conditions Ta Typ. Max Units
I
DD
V
DDANA
Differential mode fs = 1 Msps / Reference buffer disabled / BIASREFBUF = '111', BIASREFCOMP = '111'
V
DDANA
= V
REF
= 3.0V
Max 85°C Typ 25°C 279 318 µA
fs = 1 Msps / Reference buffer enabled / BIASREFBUF = '111', BIASREFCOMP = '111'
V
DDANA
= V
REF
= 3.0V
482 653
fs = 10 ksps / Reference buffer disabled / BIASREFBUF = '111', BIASREFCOMP = '111'
V
DDANA
= V
REF
= 3.0V
28 45
fs = 10 ksps / Reference buffer enabled / BIASREFBUF = '111', BIASREFCOMP = '111'
V
DDANA
= V
REF
= 3.0V
241 397
Single Ended mode fs = 1 Msps / Reference buffer disabled / BIASREFBUF = '111', BIASREFCOMP = '111'
V
DDANA
= V
REF
= 3.0V
Max 85°C Typ 25°C 307 348 µA
fs = 1 Msps / Reference buffer enabled / BIASREFBUF = '111', BIASREFCOMP = '111'
V
DDANA
= V
REF
= 3.0V
499 681
fs = 10 ksps / Reference buffer disabled / BIASREFBUF = '111', BIASREFCOMP = '111'
V
DDANA
= V
REF
= 3.0V
38 60
fs = 10 ksps / Reference buffer enabled / BIASREFBUF = '111', BIASREFCOMP = '111'
V
DDANA
= V
REF
= 3.0V
245 400
54.10.5 Digital to Analog Converter (DAC) Characteristics
Table 54-28. Operating Conditions
(1)
Symbol
Parameters Conditions Min. Typ. Max. Unit
Res Resolution - - - 12 bits
clk Internal DAC Clock frequency - - - 12 MHz
fs_dac Sampling frequency clk/12, CCTRL=0x0 (Low Power) - - 10 ksps
clk/12, CCTRL=0x2 (High Power) - - 1 Msps
V
OUTmin
Min. Output Voltage - - - 0.15 V
V
OUTmax
Max. Output Voltage - V
DDANA
-0.15 - -
V
REF
External Reference input CTRLB.REFSEL[1:0]=0x2 (VREFAB) 1 - V
DDANA
-0.15 V
CTRLB.REFSEL[1:0]=0x0 (VREFAU) 1 - V
DDANA
C
VREF
External decoupling capacitor - - 220 - nF
C
LOAD
Output capacitor load - - - 50 pF
R
LOAD
Output resistance load - 5 - - kΩ
t
s
Settling time For reaching ±1LSB of the final value.
Step size < 500 LSB - C
load
= 50pF
- - 1 µs
t
s_FS
Settling time 0x080 to 0xF7F For reaching ±1LSB of the final value.
Step size from 0% to 100% - C
load
= 50pF
- 5 7 µs
SAM D5x/E5x Family Data Sheet
Electrical Characteristics at 85°C
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 2005