Datasheet

• Idle, Standby, Hibernate, Backup, and Off sleep modes
• SleepWalking peripherals
• Battery backup support
• Embedded Buck/LDO regulator supporting on-the-fly selection
High-Performance Peripherals
• 32-channel Direct Memory Access Controller (DMAC)
– Built-in CRC with memory CRC generation/monitor hardware support
• Up to two SD/MMC Host Controller (SDHC)
– Up to 50 MHz operation
– 4-bit or 1-bit interface
– Compatibility with SD and SDHC memory card specification version 3.01
– Compatibility with SDIO specification version 3.0
– Compliant with JDEC specification, MMC memory cards V4.51
• One Quad I/O Serial Peripheral Interface (QSPI)
– eXecute-In-Place (XIP) support
– Dedicated AHB memory zone
• One Ethernet MAC (SAM E53 and SAM E54)
– 10/100 Mbps in MII and RMII with dedicated DMA
– IEEE
®
1588 Precision Time Protocol (PTP) support
– IEEE 1588 Time Stamping Unit (TSU) support
– IEEE802.3AZ energy efficiency support
– Support for 802.1AS and 1588 precision clock synchronization protocol
– Wake on LAN support
• Up to two Controller Area Network (CAN) (that is., SAM E51 and SAM E54)
– Support for CAN 2.0A/CAN 2.0B and CAN-FD (ISO 11898-1:2016)
• One Full-Speed (12 Mbps) Universal Serial Bus (USB) 2.0 interface
– Embedded host and device function
– Eight endpoints
– On-chip transceiver with integrated serial resistor
System Peripherals
• 32-channel Event System
• Up to eight Serial Communication Interfaces (SERCOM), each configurable to operate as either:
– USART with full-duplex and single-wire half-duplex configuration
– ISO7816
– I
2
C up to 3.4 MHz
– SPI
– LIN master/slave
– RS485
– SPI inter-byte space
• Up to eight 16-bit Timers/Counters (TC) each configurable as:
– 16-bit TC with two compare/capture channels
– 8-bit TC with two compare/capture channels
SAM D5x/E5x Family Data Sheet
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 2