Datasheet

...........continued
Symbol Description Max. Units
f
GCLK_CANx, x = {0, 1}
CANx input clock frequency 100 MHz
f
GCLK_USB
USB input clock frequency 60 MHz
f
GCLK_I2S
I2S input clock frequency 100 MHz
f
GCLK_SDHCx_SLOW, x = {0, 1}
Common SDHCx slow input clock frequency 12 MHz
f
GCLK_SDHCx_CORE, x = {0, 1}
SDHCx input clock frequency 150 MHz
f
GCLK_TCCx, x = {0, ... , 4}
TCCx input clock frequency 200 MHz
f
GCLK_TCx, x = {0, ... , 3}
TC0, TC1, TC2, TC3 input clock frequency 200 MHz
f
GCLK_TCx, x = {4, ... , 7}
TC4, TC5, TC6, TC7 input clock frequency 100 MHz
f
GCLK_PDEC
PDEC input clock frequency 200 MHz
f
GCLK_CCL
CCL input clock frequency 100 MHz
f
GCLK_GCLKIN
External GCLK input clock frequency 50 MHz
f
GCLK_CM4_TRACE
CM4 Trace input clock frequency 120 MHz
f
GCLK_AC
AC digital input clock frequency 100 MHz
f
GCLK_ADCx, x = {0, 1}
ADCx input clock frequency 100 MHz
f
GCLK_DAC
DAC input clock frequency 100 MHz
Note:
1. These values are based on simulation. They are not covered by production test limits or
characterization.
54.7 Power Consumption
The values in this section are measured values of power consumption under the following conditions,
except where noted:
• Operating Conditions
– CPU is running on Flash with automatic wait state
– Low-power cache enabled.
– BOD33 is disabled
– I/Os are inactive input mode with input trigger disabled
• Oscillators
– XOSC0 (crystal oscillator) running with external 32 MHz crystal
– XOSC32K (32 kHz crystal oscillator) running with external 32 kHz crystal in LP mode
– FDPLL is using XOSC32K as reference
– DFLL is using XOSC32K as reference
SAM D5x/E5x Family Data Sheet
Electrical Characteristics at 85°C
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1990