Datasheet

53.8.8 Status
Name: STATUS
Offset: 0x0C
Reset: 0x0040
Property: Read-Synchronized, Write-Synchronized
Bit 15 14 13 12 11 10 9 8
CCBUFV1 CCBUFV0 FILTERBUFV PRESCBUFV
Access
R R R R
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
DIR STOP HERR WINERR MPERR IDXERR QERR
Access
R R RW RW RW RW RW
Reset 0 1 0 0 0 0 0
Bits 12, 13 – CCBUFV Compare Channel x Buffer Valid
The bit is set when a new value is written to the corresponding CCBUF register.
The bit is cleared by writing a '1' to the corresponding location or automatically cleared on an UPDATE
condition.
Bit 9 – FILTERBUFV Filter Buffer Valid
This bit is set when a new value is written to the PRESCALERBUF register.
The bit is cleared by writing a '1' to the corresponding location or automatically cleared on an UPDATE
condition.
This bit is always read '0' when COUNTER operation mode is selected.
Bit 8 – PRESCBUFV Prescaler Buffer Valid
This bit is set when a new value is written to the PRESC register.
The bit is cleared by writing a '1' to the corresponding location or automatically cleared on an UPDATE
condition.
Bit 7 – DIR Direction Status Flag
This bit reflects the HALL/QDEC direction.
in COUNTER mode, this bits is always read '0'.
Value Description
0
Clockwise direction.
1
Counter-clockwise direction.
Bit 6 – STOP Stop
This bit reflects the HALL/QDEC decoding status.
In COUNTER mode, this bits is always read '0'.
Value Description
0
PDEC/HALL decoding is running.
1
PDEC/HALL decoding is stopped.
Bit 5 – HERR Hall Error Flag
This flag is set when an invalid HALL code is detected.
SAM D5x/E5x Family Data Sheet
PDEC – Position Decoder
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1974