Datasheet

53.8.6 Interrupt Enable Set
Name: INTENSET
Offset: 0x09
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to change this register without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Bit 7 6 5 4 3 2 1 0
MC1 MC0 VLC DIR ERR OVF
Access
RW RW RW RW RW RW
Reset 0 0 0 0 0 0
Bits 4, 5 – MC Channel x Compare Match Enable
Writing a '0' to MCx has no effect.
Writing a '1' to MCx will set the corresponding Match Channel x Interrupt Disable/Enable bit, which
enables the Match Channel x interrupt.
Value Description
0
The Match Channel x interrupt is disabled.
1
The Match Channel x interrupt is enabled.
Bit 3 – VLC Velocity Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Velocity Interrupt Disable/Enable bit, which enables the Velocity
interrupt.
This bit has no effect when COUNTER operation mode is selected.
Value Description
0
The Velocity interrupt is disabled.
1
The Velocity interrupt is enabled.
Bit 2 – DIR Direction Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Direction Change Interrupt Disable/Enable bit, which enables the
Direction Change interrupt.
This bit has no effect when COUNTER operation mode is selected.
Value Description
0
The Direction Change interrupt is disabled.
1
The Direction Change interrupt is enabled.
Bit 1 – ERR Error Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Error Interrupt Disable/Enable bit, which enables the Error interrupt.
Value Description
0
The Error interrupt is disabled.
1
The Error interrupt is enabled.
Bit 0 – OVF Overflow/Underflow Interrupt Enable
Writing a '0' to this bit has no effect.
SAM D5x/E5x Family Data Sheet
PDEC – Position Decoder
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1971