Datasheet

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6. I/O Multiplexing and Considerations
16.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
16.5.1 I/O Lines
Not applicable.
16.5.2 Power Management
The Reset Controller module is always on.
16.5.3 Clocks
The RSTC bus clock (CLK_RSTC_APB) can be enabled and disabled in the Main Clock Controller.
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15. MCLK – Main Clock
15.6.2.6 Peripheral Clock Masking
16.5.4 DMA
Not applicable.
16.5.5 Interrupts
Not applicable.
16.5.6 Events
Not applicable.
16.5.7 Debug Operation
When the CPU is halted in debug mode, the RSTC continues normal operation.
16.5.8 Register Access Protection
All registers with write access can be optionally write-protected by the Peripheral Access Controller
(PAC).
Note: Optional write protection is indicated by the "PAC Write Protection" property in the register
description.
Write protection does not apply for accesses through an external debugger.
16.5.9 Analog Connections
Not applicable.
16.6 Functional Description
16.6.1 Principle of Operation
The Reset Controller collects the various Reset sources and generates Reset for the device.
SAM D5x/E5x Family Data Sheet
RSTC – Reset Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 197