Datasheet

53.8.4 Event Control
Name: EVCTRL
Offset: 0x06
Reset: 0x0000
Property: Enable-Protected, PAC Write-Protection
Bit 15 14 13 12 11 10 9 8
MCEO1 MCEO0 VLCEO DIREO ERREO OVFEO
Access
RW RW RW RW RW RW
Reset 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
EVEI[2:0] EVINV[2:0] EVACT[1:0]
Access
RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bits 12, 13 – MCEO Match Channel x Event Output Enable
These bits control whether event match on channel x is enabled or not and generated for every match.
Value Description
0
Match event on channel x is disabled and will not be generated.
1
Match event on channel x is enabled and will be generated for every compare.
Bit 11 – VLCEO Velocity Output Event Enable
This bit is used to enable the velocity event. When enabled, an event level will be generated for each
change on the qualified PDEC phases.
This bit has no effect when COUNTER operation mode is selected.
Value Description
0
VLC output event is disabled and will not be generated.
1
VLC output is enabled and will be generated for every valid velocity condition.
Bit 10 – DIREO Direction Output Event Enable
This bit is used to enable the Direction event. When enabled, an event level output is generated to report
the rotation direction.
Value Description
0
DIR output event is disabled and will not be generated.
1
DIR output is enabled and changes the level when the rotation direction changes.
Bit 9 – ERREO Error Output Event Enable
This bit enables the output of the Error event (ERR).
Value Description
0
ERR Event output is disabled.
1
ERR Event output is enabled.
Bit 8 – OVFEO Overflow/Underflow Output Event Enable
This bit is used to enable the Overflow/Underflow event. When enabled, an event will be generated when
the Counter overflows/underflows.
Value Description
0
Overflow/Underflow event is disabled and will not be generated.
SAM D5x/E5x Family Data Sheet
PDEC – Position Decoder
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1967