Datasheet

53.8.2 Control B Clear
Name: CTRLBCLR
Offset: 0x04
Reset: 0x00
Property: PAC Write-Protection, Read-Synchronized, Write-Synchronized
This register allows the user to change this register without doing a read-modify-write operation. Changes
in this register will also be reflected in the Control B Set (CTRLBSET) register.
Bit 7 6 5 4 3 2 1 0
CMD[2:0] LUPD
Access
RW RW RW RW
Reset 0 0 0 0
Bits 7:5 – CMD[2:0] Command
These bits can be used for software control of the PDEC. When a command has been executed, the
CMD bit group will read back zero. The commands are executed on the next prescaled GCLK_PDEC
clock cycle.
Writing a zero to this bit group has no effect.
Writing a valid value to these bits will clear the corresponding pending command.
Writing a '0' to these bits has no effect.
Writing a '1' to an individual bit will clear the corresponding bit.
Value Name Description
0
NONE No action
1
RETRIGGER Force a counter restart or re-trigger
2
UPDATE Force update of double buffered registers
3
READSYNC Force a read synchronization of COUNT
4
START Start QDEC/HALL
5
STOP Stop QDEC/HALL
Bit 1 – LUPD Lock Update
This bit controls the update operation of the PDEC buffered registers.
When CTRLB.LUPD is set, no any update of the registers with value of its buffered register is performed
on hardware UPDATE condition. Locking the update ensures that all buffer registers are valid before an
hardware update is performed. After all the buffer registers are loaded correctly, the buffered registers
can be unlocked.
Writing a '0' to this bit has no effect.
Writing a '1' to this will disable the lock update.
Value Description
0
The PRESCBUF, FILTERBUF and CCBUFx buffer registers value are copied into CCx and
PER registers on hardware update condition.
1
The PRESCBUF, FILTERBUF and CCBUFx buffer registers value are not copied into CCx
and PER registers on hardware update condition.
SAM D5x/E5x Family Data Sheet
PDEC – Position Decoder
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1965