Datasheet

Value Description
0
Auto Lock is disabled.
1
Auto Lock is enabled.
Bits 10:8 – CONF[2:0] PDEC Configuration
These bits define the PDEC configuration.
Outside of QDEC mode, these bits have no effect.
These bits are not synchronized.
Value Name Description
0
X4 Quadrature decoder direction
1
X4S Secure Quadrature decoder direction
2
X2 Decoder direction
3
X2S Secure decoder direction
4
AUTOC Auto correction mode
Bit 6 – RUNSTDBY Run in Standby
This bit is used to keep the PDEC running in standby mode.
This bit is not synchronized.
Value Description
0
The PDEC is halted in standby.
1
The PDEC continues to run in standby.
Bits 3:2 – MODE[1:0] Operation Mode
These bits select one of the QDEC, HALL, COUNTER modes.
These bits are not synchronized.
Value Name Description
0x0
QDEC QDEC operating mode
0x1
HALL HALL operating mode
0x2
COUNTER COUNTER operating mode
Bit 1 – ENABLE Enable
Due to synchronization, there is delay between writing CTRLA.ENABLE until the peripheral is enabled/
disabled. The value written to CTRLA.ENABLE will read back immediately, and the Enable
Synchronization Busy bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set.
SYNCBUSY.ENABLE will be cleared when the operation is complete.
Value Description
0
The peripheral is disabled.
1
The peripheral is enabled.
Bit 0 – SWRST Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets all registers in the PDEC (except DBGCTRL) to their initial state, and the
PDEC will be disabled.
Writing a '1' to CTRLA.SWRST will always take precedence; all other writes in the same write-operation
will be discarded.
Due to synchronization, there is a delay from writing CTRLA.SWRST until the Reset is complete.
CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the Reset is complete.
Value Description
0
There is no Reset operation ongoing.
SAM D5x/E5x Family Data Sheet
PDEC – Position Decoder
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1963