Datasheet

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ANGULAR[2:0] Angular counter Revolution counter
0x2 COUNTER[0:10] COUNTER[11:15]
0x3 COUNTER[0:11] COUNTER[12:15]
0x4 COUNTER[0:12] COUNTER[13:15]
0x5 COUNTER[0:13] COUNTER[14:15]
0x6 COUNTER[0:14] COUNTER[15]
0x7 COUNTER[0:15] no revolution counter
Bits 20, 21, 22 – PINVEN IO Pin x Invert Enable
When this bit is written to '1', the corresponding input pin active level is inverted. This bit has no effect if
PINENx bit is zero.
In COUNTER mode only PINVEN[0] is significant.
This bit is not synchronized.
Value Description
0
Pin active level is not inverted.
1
Pin active level is inverted.
Bits 16, 17, 18 – PINEN PDEC Input From Pin x Enable
This bit enables the IO pin x as signal input.
In COUNTER mode, only PINVEN[0] is significant.
This bit is not synchronized.
Value Description
0
Event line is the signal input.
1
I/O pin is the signal input.
Bit 15 – PEREN Period Enable
This bit is used to enable the CC0 register as counter period.
This bit is not synchronized.
Value Description
0
Period register function is disabled.
1
CC0 is acting as counter period register.
Bit 14 – SWAP PDEC Phase A and B Swap
This bit is used to swap input source of signal 0 and 1.
In COUNTER mode this bit has no effect.
This bit is not synchronized.
Value Description
0
The input sources of signal 0 and 1 are not swapped.
1
The input sources of signal 0 and 1 are swapped.
Bit 11 – ALOCK Auto Lock
When this bit is set, the Lock Update bit in Control B register (CTRLB.LUPD) is set by hardware when an
UPDATE condition is detected.
This bit is not synchronized.
SAM D5x/E5x Family Data Sheet
PDEC – Position Decoder
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1962