Datasheet

53.8.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected
Bit 31 30 29 28 27 26 25 24
MAXCMP[3:0] ANGULAR[2:0]
Access
RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
PINVEN2 PINVEN1 PINVEN0 PINEN2 PINEN1 PINEN0
Access
RW RW RW RW RW RW
Reset 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
PEREN SWAP ALOCK CONF[2:0]
Access
RW RW RW RW RW RW
Reset 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
RUNSTDBY MODE[1:0] ENABLE SWRST
Access
RW RW RW RW W
Reset 0 0 0 0 0
Bits 31:28 – MAXCMP[3:0] Maximum Consecutive Missing Pulses
These bits define the threshold for the maximum consecutive missing pulses in AUTOC configuration of
the QDEC mode.
Outside of AUTOC configuration of QDEC mode, these bits have no effect.
These bits are not synchronized.
Bits 26:24 – ANGULAR[2:0] Angular Counter Length
In QDEC mode, these bits define the size of the Angular counter within COUNT. Angular counter size is
equal to CTRLA.ANGULAR+9. The remaining MSB of the COUNTER register are used for counting
revolutions.
For example, CTRLA.ANGULAR=0 defines the 9 LSB of COUNT as Angular counter and the residual 7
MSB of COUNT as Revolution counter. CTRLA.ANGULAR=7 will define a 16-bit Angular counter and no
Revolution counter.
Outside of QDEC mode, these bits have no effect.
These bits are not synchronized.
Table 53-1. Angular and Revolution Counters in COUNTER Register
ANGULAR[2:0] Angular counter Revolution counter
0x0 COUNTER[0:8] COUNTER[9:15]
0x1 COUNTER[0:9] COUNTER[10:15]
SAM D5x/E5x Family Data Sheet
PDEC – Position Decoder
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1961