Datasheet

Table Of Contents

...........continued

Offset Name Bit Pos.

0x28

...

0x2F

Reserved

0x30 CCBUF0

7:0 CCBUF[7:0]

15:8 CCBUF[15:8]

23:16

31:24

0x34 CCBUF1

7:0 CCBUF[7:0]

15:8 CCBUF[15:8]

23:16

31:24

53.8 Register Description

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the

8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be

accessed directly.

Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC

write protection is denoted by the "PAC Write-Protection" property in each individual register description.

For details, refer to 53.5.8 Register Access Protection.

Some registers are synchronized when read and/or written. Synchronization is denoted by the "Write-

Synchronized" or the "Read-Synchronized" property in each individual register description. For details,

refer to 53.6.7 Synchronization.

SAM D5x/E5x Family Data Sheet

PDEC – Position Decoder

Datasheet

DS60001507E-page 1960