Datasheet

53.6.4 Interrupts
The PDEC has the following interrupt sources:
• Overflow/Underflow: OVF
• Compare Channels: COMPx
• Error: ERR
• Velocity: VLC. This interrupt is available only in QDEC and HALL operation modes.
• Direction: DIR. This interrupt is available only in QDEC and HALL operation modes.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status
and Clear register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be
individually enabled by writing a '1' to the corresponding bit in the Interrupt Enable Set register
(INTENSET), and disabled by writing a '1' to the corresponding bit in the Interrupt Enable Clear register
(INTENCLR).
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled.
The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the
PDEC is reset. See the INTFLAG register description for details on how to clear interrupt flags.
The user must read the INTFLAG register to determine which interrupt condition is present.
Note: Interrupts must be globally enabled for interrupt requests to be generated.
53.6.5 Events
The PDEC can generate the following output events:
• Overflow/Underflow: OVF
• Channel x Compare Match: MCx
• Error: ERR
• Velocity: VLC. This interrupt is available only in QDEC and HALL operation modes.
• Direction: DIR. This interrupt is available only in QDEC and HALL operation modes.
Writing a '1' to an Event Output bit in the Event Control register (EVCTRL.MCEO) enables the
corresponding output event. Writing a '0' to this bit disables the corresponding output event.
Related Links
31. EVSYS – Event System
53.6.6 Sleep Mode Operation
The PDEC can be configured to operate in any sleep mode. To be able to run in standby, the RUNSTDBY
bit in the Control A register (CTRLA.RUNSTDBY) must be written to '1'. The PDEC can wake up the
device using interrupts from any sleep mode or perform actions through the Event System.
53.6.7 Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers
need to be synchronized when written or read.
The following bits are synchronized when written:
• Software Reset bit in the Control A register (CTRLA.SWRST)
• Enable bit in the Control A register (CTRLA.ENABLE)
The following registers need synchronization when written:
SAM D5x/E5x Family Data Sheet
PDEC – Position Decoder
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1957