Datasheet

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• The filter output value is checked to be a valid Hall value. If an invalid Hall code is reported, the Hall

Error bit in Status register will be set (STATUS.HERR).

• The MC0 Interrupt Flag bit is set (INTFLAG.MC0) if CC0[2:0] matches the filter output value. An

optional compare match interrupt or Event output is generated on the same condition detection.

• The window counter is checked to be between CC0[MSB] and CC1[MSB] value, and reset to 0 value.

If an error is detected, the Window Error bit in Status register (STATUS.WINERR) is set.

• The delay counter is started, and MC0 optional interrupt or event is generated when the delay

counter matches CC0[LSB].

Any error condition will set the Error Interrupt Flag (INTFLAG.ERR). An optional interrupt or event output

is generated on the same condition detection.

Figure 53-9. Hall Waveforms

Counter(MSB)

101 001 101 100 110 010 011 000

CC0(MSB)

CC1(MSB)

State

ERR

VLC Event

OVF Event

DIR Event

DIR Interrupt

MC0 Event

53.6.3.2 Counter Operation Mode

Depending on the mode of operation, the counter (Counter Value register COUNT) is cleared, reloaded,

or incremented at each counter clock input.

The counter will count for each clock tick until it reaches TOP. When TOP is reached, the counter will be

set to zero on the next clock input.

This comparison will set the Overflow Interrupt Flag in the Interrupt Flag Status and Clear register

(INTFLAG.OVF) and can be used to trigger an interrupt or an event.

It is possible to change the counter value when the counter is running. The write access has higher

priority than count, or clear. The COUNT value will always be zero when starting the PDEC, unless a

different value has been written to it, or the PDEC has been disabled at a value other than zero. Due to

asynchronous clock domains, the internal counter settings are written once the synchronization is

complete.