Datasheet

ManualsBrandsSeeedStudio ManualsInternet of Things (IoT)Wio Terminal ATSAMD51 Core w/ Realtek RTL8720DN BLE 5 & Wi-Fi 2.4G/5G Dev Board

1951

Table Of Contents

53.6.2.6.4 Missing Pulse Detection and Auto-Correction

The PDEC embeds circuitry to detect and correct errors that may result from contamination on optical

disks or other sources producing quadrature phase signals.

The auto-correction works in QDEC X4 mode only. A missing pulse on a phase signal is automatically

detected, and the pulse count reported in the Angular part of COUNT is automatically corrected.

There is no autocorrection if both phase signals are affected at the same location on the input signals,

because the autocorrection requires a valid phase signal to detect contamination on the other phase

signal.

If the quadrature source is undamaged, the number of pulses counted for a predefined period of time

must be the same with or without detection and auto-correction. Therefore, if the measurement results

differ, a contamination exists on the source producing the quadrature signals. This does not substitute the

measurements of the number of pulses between two index pulses (if available) but provides an additional

method to detect damaged quadrature sources.

When the source providing quadrature signals is strongly damaged, potentially leading to a number of

consecutive missing pulses greater than 1, the quadrature decoder processing may be affected.

The Maximum Consecutive Missing Pulses bits in Control A register (CTRLA.MAXCMP) define the

maximum acceptable number of consecutive missing pulses. If the limit is reached, the Missing Pulse

Error flag in Status register (STATUS.MPERR) is set. The Error Interrupt flag is set (INTFLAG.ERR) and

an optional interrupt can be generated.

Note: When the MAXCMP value is zero, the MPERR error flag is never set.

53.6.3 Additional Features

53.6.3.1 HALL Operation Mode

In HALL operation mode, control logic signal 0, 1 and 2 inputs represent the phase A, B and C of a Hall

sensor, respectively.

A programmable delayed event can be generated to update a TCC pattern generator.

Figure 53-8. HALL Block Diagram

Hall

Decoder

Velocity Clock

Direction Change Detection

Error Detection

Reset

OVF (Interrupt/Event)

MC0 (Interrupt/Event)

MC1 (Interrupt/Event)

CC0[2:0]

Hall Code Trigger

CC1(MSB)

Window Max

VLC (Interrupt/Event)

DIR (Interrupt/Event)

ERR (Interrupt/Event)

COUNT(MSB)

Window Counter

COUNT(LSB)

Delay Counter

CC1[2:0]

(Unused)

CC0(MSB)

Window Min

sync

syncsync

Filter

Phase A

Phase B

Phase C

Signal 0

Signal 1

Signal 2