Datasheet

Figure 53-5. Position and Rotation Measurement
PhaseA
DIR Event
PhaseB
Index
Angle OVF
ERR
Anglular
Counter
Revolution
Counter
CC1 (LSB)
CC1 (MSB)
MC1 Event
CC0 (LSB)
in Q4 and Q4S configuration, a valid index is detected when the three inputs (PhaseA, PhaseB and
Index) are at low level.
In Q2 and Q2S configuration, a valid index is detected when the two inputs (Count and Index) are at low
level.
in Q2 and Q4 configuration, depending on current detected direction, Index will reset or reload the
Angular counter and increment or decrement the Revolution counter.
In Q2S and Q4S configuration, the Angular counter is reset on the first Index occurrence after the PDEC
decoding is enabled. When any next Index occurrence does not match an Angular counter overflow or
underflow, the Index Error flag in Status register is set (STATUS.IDXERR). The Error Interrupt Flag is set
(INTFLAG.ERR) and an optional interrupt can be generated.
An Index Error is also generated after the PDEC decoding is enabled and no Index has been detected
after one Angular counter revolution.
53.6.2.6.2 Direction Status and Change Detection
The direction (DIR) status can be directly read anytime in the STATUS register (STATUS.DIR). The
polarity of the direction flag status depends of the input signal swap and active level configuration.
Each time a rotation direction change is detected, the Direction Change Interrupt Flag is set
(INTFLAG.DIR) and an optional interrupt can be generated. The same interrupt condition is source of
Direction event output.
SAM D5x/E5x Family Data Sheet
PDEC – Position Decoder
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1952