Datasheet

The PDEC is enabled by writing a '1' to the Enable bit in the Control A register (CTRLA.ENABLE). The
PDEC is disabled by writing a '0' to CTRLA.ENABLE.
In QDEC or HALL operation modes, PDEC decoding is enabled writing a START command in the Control
B Set register (CTRLBSET.CMD=START). The PDEC decoding is disabled writing a STOP command in
the Control B Set register (CTRLBSET.CMD=STOP).
The PDEC is reset by writing a '1' to the Software Reset bit in the Control A register (CTRLA.SWRST). All
registers in the PDEC, except DBGCTRL, will be reset to their initial state, and the PDEC will be disabled.
The PDEC should be disabled before the PDEC is reset to avoid undefined behavior.
53.6.2.3 Prescaler Selection
The GCLK_PDEC is fed into the internal prescaler. Prescaler outputs from 1 to 1/1024 are directly
available for selection by the counter and all selections are available in Prescaler register (PRESC). If the
prescaler value is higher than 0x01, the counter update condition is executed on the next prescaled clock
pulse.
If the counter is set to count events, the internal prescaler is bypassed and the GCLK_PDEC clock is
automatically selected during operation. The prescaler clock is also enabled when the input filtering is
required.
Figure 53-2. Prescaler Selection
EVENT
COUNT
Prescaler
PRESC
EVACT
GCLK_PDEC
GCLK_PDEC /
{1,2,4,8,64,256,1024 }
CLK_PDEC
53.6.2.4 Input Selection and Filtering
The QDEC and HALL operations require three inputs, as shown in the Block Diagram. Each input can
either be a dedicated I/O pin or an Event system channel. This is selected by writing to the corresponding
Event x Enable bit in the Event Control register (EVCTRL.EVEIx) or Pin x Enable bit in the Control A
register (CTRLA.PINENx).
The I/O input pin active level can be inverted by writing to the corresponding Pin x Inversion Enable bit in
Control A register (CTRLA.PINVENx). In the same way, the event input active level can be inverted by
writing to the corresponding Inverted Event x Input Enable bit in Event Control register
(EVCTRL.EVINVx).
All input signals can be filtered before they are fed into the control logic. The FILTER register is used to
configure the minimum duration for which the input signal has to be valid. The input signal minimum
duration must be FILTER* t
GCLK_PDEC
.
Figure 53-3. Input Signal Filtering
Pescaled Clock
Filter Out
(Signal 0, Signal 1, Signal 2)
SAM D5x/E5x Family Data Sheet
PDEC – Position Decoder
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1950