Datasheet

18. PM – Power Manager
53.5.3 Clocks
A generic clock (GCLK_PDEC) is required to clock the PDEC. This clock must be configured and enabled
in the generic clock controller before using the PDEC.
This generic clock is asynchronous to the bus clock (CLK_PDEC_APB). Due to this asynchronicity, writes
to certain registers will require synchronization between the clock domains.
Related Links
14. GCLK - Generic Clock Controller
13.3 Register Synchronization
53.5.4 DMA
Not applicable.
53.5.5 Interrupts
The interrupt request line is connected to the Interrupt Controller. In order to use interrupt requests of this
peripheral, the Interrupt Controller (NVIC) must be configured first. Refer to Nested Vector Interrupt
Controller for details.
Related Links
10.2 Nested Vector Interrupt Controller
10.2.1 Overview
10.2.2 Interrupt Line Mapping
53.5.6 Events
The events of this peripheral are connected to the Event System.
Related Links
31. EVSYS – Event System
53.5.7 Debug Operation
When the CPU is halted in debug mode the PDEC will halt normal operation. The PDEC can be forced to
continue operation during debugging. Refer to DBGCTRL register for details.
53.5.8 Register Access Protection
All registers with write access can be write-protected optionally by the Peripheral Access Controller
(PAC), except for the following registers:
• Interrupt Flag register (INTFLAG)
• Filter register (FILTER)
• Precaler register (PRESC)
• Compare x Value register (CCx)
• Channel x Compare Buffer Value register (CCBUFx)
• Status register (STATUS)
Optional write protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write
Protection" property in each individual register description.
PAC write protection does not apply to accesses through an external debugger.
SAM D5x/E5x Family Data Sheet
PDEC – Position Decoder
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1948