Datasheet

15.8.11 APBD Mask
Name: APBDMASK
Offset: 0x20
Reset: 0x00000000
Property: PAC Write-Protection
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
PCC I2S DAC ADCn1
Access
R/W R/W R R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
ADCn0 TC7 TC6 TCC4 SERCOM7 SERCOM6 SERCOM5 SERCOM4
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 11 – PCC PCC APBD Mask Clock Enable
Value Description
0
The APBD clock for the PCC is stopped.
1
The APBD clock for the PCC is enabled.
Bit 10 – I2S I2S APBD Mask Clock Enable
Value Description
0
The APBD clock for the I2S is stopped.
1
The APBD clock for the I2S is enabled.
Bit 9 – DAC DAC APBD Mask Clock Enable
Value Description
0
The APBD clock for the DAC is stopped.
1
The APBD clock for the DAC is enabled.
Bits 7, 8 – ADCn ADCn APBD Mask Clock Enable
Value Description
0
The APBD clock for the ADCn is stopped.
1
The APBD clock for the ADCn is enabled.
Bits 5, 6 – TC TCn APBD Mask Clock Enable
SAM D5x/E5x Family Data Sheet
MCLK – Main Clock
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 194