Datasheet

52.8.3 Interrupt Disable Register
Name: IDR
Offset: 0x08
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
RXBUFF ENDRX OVRE DRDY
Access
W W W W
Reset 0 0 0 0
Bit 3 – RXBUFF Reception Buffer Full Interrupt Disable
Writing a '1' to this register disables the Reception Buffer Full interrupt.
Writing a '0' has no effect.
Bit 2 – ENDRX End of Reception Transfer Interrupt Disable
Writing a '1' to this register disables the End of Reception Transfer interrupt.
Writing a '0' has no effect.
Bit 1 – OVRE Overrun Error Interrupt Disable
Writing a '1' to this register disables the Overrun Error interrupt.
Writing a '0' has no effect.
Bit 0 – DRDY Data Ready Interrupt Disable
Writing a '1' to this register disables the Data Ready interrupt.
Writing a '0' has no effect.
SAM D5x/E5x Family Data Sheet
PCC - Parallel Capture Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1939