Datasheet

52.8.1 PCC Mode Register
Name: MR
Offset: 0x00
Reset: 0x00000000
Property: -
This register can only be written if the WPEN bit is cleared in the Write Protection Mode Register.
Bit 31 30 29 28 27 26 25 24
CID[1:0]
Access
R/W R/W
Reset 0 0
Bit 23 22 21 20 19 18 17 16
ISIZE[2:0]
Access
R/W R/W R/W
Reset 0 0 0
Bit 15 14 13 12 11 10 9 8
FRSTS HALFS ALWYS SCALE
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
DSIZE[1:0] PCEN
Access
R/W R/W R/W
Reset 0 0 0
Bits 31:30 – CID[1:0] Clear If Disabled
Clears status flags if disabled. These bits are useful to re-initialize the internal mechanism of the PCC to
avoid corrupted data due to glitches. Each time a falling edge of the selected DEN1 or DEN2 signal is
detected, the internal mechanism of the PCC is re-initialized to avoid alignment issues.
Value Description
0x0
Clear not enabled
0x1
Clear on falling edge on DEN1 enabled
0x2
Clear on falling edge on DEN2 enabled
0x3
Clear on falling edge on either DEN1 or DEN2 enabled
Bits 18:16 – ISIZE[2:0] Input Data Size
Value Name Description
0x0
8_BITS Input data bus size is 8 bits
0x1
10_BITS Input data bus size is 10 bits
0x2
12_BITS Input data bus size is 12 bits
0x3
14_BITS Input data bus size is 14 bits
Bit 11 – FRSTS First Sample
This bit is useful only if the HALFS bit is set to 1. If data are numbered in the order that they are received
with an index from 0 to n.
SAM D5x/E5x Family Data Sheet
PCC - Parallel Capture Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1936