Datasheet

52.7 Register Summary
Offset Name Bit Pos.
0x00 MR
7:0 DSIZE[1:0] PCEN
15:8 FRSTS HALFS ALWYS SCALE
23:16 ISIZE[2:0]
31:24 CID[1:0]
0x04 IER
7:0 RXBUF ENDRX OVRE DRDY
15:8
23:16
31:24
0x08 IDR
7:0 RXBUFF ENDRX OVRE DRDY
15:8
23:16
31:24
0x0C IMR
7:0 RXBUFF ENDRX OVRE DRDY
15:8
23:16
31:24
0x10 ISR
7:0 RXBUFF ENDRX OVRE DRDY
15:8
23:16
31:24
0x14 RHR
7:0 RDATA[7:0]
15:8 RDATA[15:8]
23:16 RDATA[23:16]
31:24 RDATA[31:24]
0x18
...
0xDF
Reserved
0xE0 WPMR
7:0 WPEN
15:8 WPKEY[7:0]
23:16 WPKEY[15:8]
31:24 WPKEY[23:16]
0xE4 WPSR
7:0 WPVS
15:8 WPVSRC[7:0]
23:16 WPVSRC[15:8]
31:24
52.8 Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the
8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
SAM D5x/E5x Family Data Sheet
PCC - Parallel Capture Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1934