Datasheet

52.6.3 Programming Sequence
52.6.3.1 Without DMAC
1. Write the Interrupt Enable and Interrupt Disable Registers (IER and IDR) in order to configure the
PCC interrupt mask.
2. Write the Mode Register (MR) fields ISIZE, SCALE, DSIZE, ALWYS, HALFS and FRSTS in order to
configure the PCC. Do not enable the PCC in this write access.
3. Write the PCC Enable bit in the Mode Register (MR.PCEN) to '1' in order to enable the PCC. Do
not change the configuration from the previous step.
4. Wait for a Data Ready, either by polling the Data Ready flag in the Interrupt Status Register
(ISR.DRDY) or by waiting for the corresponding interrupt.
5. Check the Overrun Error flag (ISR.OVRE).
6. Read the data in the Reception Holding Register (RHR).
7. If new data are expected, go to step 4.
8. Disable the PCC by writing MR.PCEN to '0' without changing the configuration.
52.6.3.2 With DMAC
1. Write the Interrupt Enable and Interrupt Disable Registers (IER and IDR) in order to configure the
PCC interrupt mask.
2. Configure DMAC transfer in the DMAC registers.
3. Write the Mode Register (MR) fields ISIZE, SCALE, DSIZE, ALWYS, HALFS and FRSTS in order to
configure the PCC. Do not enable the PCC in this write access.
4. Write the PCC Enable bit in the Mode Register (MR.PCEN) to '1' in order to enable the PCC. Do
not change the configuration from the previous step.
5. Wait for end of transfer, indicated by the interrupt corresponding the End Receive flag in the
Interrupt Status Register (ISR.ENDRX).
6. Check the Overrun Error flag (ISR.OVRE).
7. If a new buffer transfer is expected, go to step 5.
8. Disable the PCC by writing MR.PCEN to '0' without changing the configuration.
SAM D5x/E5x Family Data Sheet
PCC - Parallel Capture Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1933