Datasheet

Once enabled, the PCC samples the data at rising edge of the sensor clock, and resynchronizes it with
the PCC clock domain.
The input data bus size can be programmed using the Input Data Size bit field (MR.ISIZE).
A re-initialization of the internal mechanism of the PCC can be automatically done by setting the CID
register when a falling edge of the DEN1 or DEN2 is detected. This feature allows glitch filtering and
prevents image de-synchronization.
The number of the data which can be read in the Reception Holding Register (RHR) can be programmed
by writing the Data Size bit field (MR.DSIZE). The PCC samples one or several sensor data, according to
the DSIZE value.
If the MR.SCALE bit is written to '1' and MR.ISIZE ≠ 0, the sampled data is automatically up-scaled to 16
bits. When the right number of data has be sampled, data are stored in the RHR, and the Data Ready
flag in the Interrupt Status Register (ISR.DRDY) is set to '1'.
The PCC can be associated with a reception channel of the DMA Controller (DMAC). This performs
reception transfer from the PCC to a memory buffer without any intervention from the CPU. Transfer
status signals from the DMAC are available in the Interrupt Status Register through the flags ISR.ENDRX
and ISR.RXBUFF.
The PCC can be configured to either comply with the sensor data enable signals, or not. If the Always
Sampling bit in the Mode Register (MR.ALWYS) is written to '0', the PCC samples the sensor data at the
rising edge of the sensor clock only if both data enable signals are active (at '1'). If ALWYS is written to
'1', the PCC samples the sensor data at the rising edge of the sensor clock, independent of the data
enable signals.
The PCC can be configured to sample the sensor data only every other time. This is particularly useful
when only the luminance Y from a YUV422 data stream of a CMOS digital image sensor is to be
sampled. If the Half Sampling bit in the Mode Register (MR.HALFS) is written to '0', the PCC samples the
sensor data as configured above. If MR.HALFS=1, the PCC samples the sensor data as configured
above (i.e. respecting the MR.ALWYS setting), but only one time out of two.
The PCC can either sample the even or odd sensor data, depending on the First Sample bit
(MR.FRSTS). If sensor data are numbered with an index from zero to n in the order they are received and
FRSTS=0, only data with an even index are sampled. For FRSTS=1, only data with an odd index are
sampled.
If data are ready in the Reception Holding Register (RHR) but it is not read before new data is stored in
RHR, an overrun error occurs: The previous data is lost and the Overrun Error flag in the Interrupt Status
Register (ISR.OVRE) is set. This flag is automatically cleared when ISR is read (reset after read).
The flags ENDRX, RXBUFF, DRDY and OVRE can be a source of the PCC interrupt.
SAM D5x/E5x Family Data Sheet
PCC - Parallel Capture Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1928