Datasheet

The interrupt request line is connected to the interrupt controller. Using the interrupts requires the
interrupt controller to be configured first. Refer to NVIC - Nested Interrupt Nested Vector Interrupt
Controller for details.
52.5.6 Events
Not applicable.
52.5.7 Debug Operation
When the CPU is halted in debug mode, the PCC will not halt normal operation.
Note: A buffer overflow condition will occur if the received data buffer is not read by CPU or CPU
DMAC.
52.5.8 Register Access Protection
To prevent any single software error from corrupting PCC behavior, certain registers in the address space
can be write-protected by setting the WPEN bit in the Write Protection Mode Register (WPMR).
If a write access to a write-protected register is detected, the WPVS flag in the Write Protection Status
Register (WPSR) is set and WPSR.WPVSRC indicates the register in which the write access has been
attempted.
The WPVS bit is automatically cleared after reading WPSR.
The following registers can be write-protected:
• PCC Mode Register
52.5.9 Analog Connections
Not applicable.
52.6 Functional Description
52.6.1 Principle of Operation
For better understanding and to ease reading, the following description uses an example with a CMOS
digital image sensor.
The CMOS digital image sensor provides a sensor clock, an 10-bit data synchronous with the sensor
clock and two data enables which are also synchronous with the sensor clock.
Figure 52-2. Parallel Capture Controller Connection with CMOS Digital Image Sensor
Parallel Capture
Controller
CMOS Digital
Image Sensor
DMAC
Data
CLK
DATA[9:0]
DEN1
DEN2
PCLK
DATA[9:0]
VSYNC
HSYNC
The PCC must be configured first, and is enabled by writing a '1' to the Parallel Capture Enable bit in the
Mode Register (MR.PCEN).
SAM D5x/E5x Family Data Sheet
PCC - Parallel Capture Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1927