Datasheet

Table Of Contents

52.5 Product Dependencies

For the Parallel Capture Controller to function as intended, other interconnected modules of the system

must be configured accordingly.

52.5.1 I/O Lines

The PCC pins may be multiplexed with the I/O lines Controller. The user must first configure the I/O

Controller to assign the PCC pins to their peripheral functions.

52.5.2 Power Management

The PCC will continue to operate in any Sleep mode where the selected source clock is running. Events

connected to the event system can trigger other operations in the system without exiting Sleep modes.

52.5.3 Clocks

The PCC bus clock (CLK_APB_PCC) is provided by the Main Clock Controller (MCLK) through the AHB-

APB D bridge. The clock is enabled and disabled by writing the PCC bit the in the APB D Mask register

(MCLK.APBDMASK.PCC). See the register description for the default state of the PCC bus clock.

For capturing operation, the external device has to provide a PCC clock signal (PCC_CLK) synchronous

to the data received ("pixel clock") through a pin. See the PORT section and the Multiplexing table for

details.

Writing any of the registers does not require the PCC_CLK to be enabled.

Important: The CLK_APB_PCC clock frequency must be at least twice the PCC_CLK

frequency.