Datasheet

15.8.10 APBC Mask
Name: APBCMASK
Offset: 0x1C
Reset: 0x00002000
Property: PAC Write-Protection
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
CCL QSPI ICM TRNG AES AC
Access
R/W R/W R/W R/W R/W R/W
Reset 0 1 0 0 0 0
Bit 7 6 5 4 3 2 1 0
PDEC TCn5 TCn4 TCCn3 TCCn2 GMAC
Access
R/W R/W R/W R/W R/W R/W
Reset 0 0 1 0 0 1
Bit 14 – CCL CCL APBC Mask Clock Enable
Value Description
0
The APBC clock for the CCL is stopped.
1
The APBC clock for the CCL is enabled.
Bit 13 – QSPI QSPI APBC Mask Clock Enable
Value Description
0
The APBC clock for the QSPI is stopped.
1
The APBC clock for the QSPI is enabled.
Bit 11 – ICM ICM APBC Mask Clock Enable
Value Description
0
The APBC clock for the ICM is stopped.
1
The APBC clock for the ICM is enabled.
Bit 10 – TRNG TRNG APBC Mask Clock Enable
Value Description
0
The APBC clock for the TRNG is stopped.
1
The APBC clock for the TRNG is enabled.
Bit 9 – AES AES APBC Mask Clock Enable
SAM D5x/E5x Family Data Sheet
MCLK – Main Clock
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 192