Datasheet

51.9.3 Interrupt Enable Clear
Name: INTENCLR
Offset: 0x0C
Reset: 0x0000
Property: PAC Write-Protection
Bit 15 14 13 12 11 10 9 8
TXUR1 TXUR0 TXRDY1 TXRDY0
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
RXOR1 RXOR0 RXRDY1 RXRDY0
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bits 12, 13 – TXURx Transmit Underrun x Interrupt Enable [x=1..0]
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Transmit Underrun x Interrupt Enable bit, which disables the Transmit
Underrun x interrupt.
Value Description
0
The Transmit Underrun x interrupt is disabled.
1
The Transmit Underrun x interrupt is enabled.
Bits 8, 9 – TXRDYx Transmit Ready x Interrupt Enable [x=1..0]
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Transmit Ready x Interrupt Enable bit, which disables the Transmit
Ready x interrupt.
Value Description
0
The Transmit Ready x interrupt is disabled.
1
The Transmit Ready x interrupt is enabled.
Bits 4, 5 – RXORx Receive Overrun x Interrupt Enable [x=1..0]
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Receive Overrun x Interrupt Enable bit, which disables the Receive
Overrun x interrupt.
Value Description
0
The Receive Overrun x interrupt is disabled.
1
The Receive Overrun x interrupt is enabled.
Bits 0, 1 – RXRDYx Receive Ready x Interrupt Enable [x=1..0]
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Receive Ready x Interrupt Enable bit, which disables the Receive
Ready x interrupt.
Value Description
0
The Receive Ready x interrupt is disabled.
1
The Receive Ready x interrupt is enabled.
SAM D5x/E5x Family Data Sheet
I2S - Inter-IC Sound Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1912