Datasheet

MCKSEL Name Description
0x0 GCLK GCLK_I2S_n is used as Master Clock n source
0x1 MCKPIN MCKn input pin is used as Master Clock n source
Bit 12 – SCKOUTINV Serial Clock Output Invert
Value Description
0
The Serial Clock n is output without inversion.
1
The Serial Clock n is inverted before being output.
Bit 11 – SCKSEL Serial Clock Select
This field selects the source of the Serial Clock n.
SCKSEL Name Description
0x0 MCKDIV Divided Master Clock n is used as Serial Clock n source
0x1 SCKPIN SCKn input pin is used as Serial Clock n source
Bit 10 – FSOUTINV Frame Sync Output Invert
Value Description
0
The Frame Sync n is output without inversion.
1
The Frame Sync n is inverted before being output.
Bit 9 – FSINV Frame Sync Invert
Value Description
0
The Frame Sync n is used without inversion.
1
The Frame Sync n is inverted before being used.
Bit 8 – FSSEL Frame Sync Select
This field selects the source of the Frame Sync n.
FSSEL Name Description
0x0 SCKDIV Divided Serial Clock n is used as Frame Sync n source
0x1 FSPIN FSn input pin is used as Frame Sync n source
Bit 7 – BITDELAY Data Delay from Frame Sync
BITDELAY Name Description
0x0 LJ Left Justified (0 Bit Delay)
0x1 I2S I2S (1 Bit Delay)
Bits 6:5 – FSWIDTH[1:0] Frame Sync Width
This field selects the duration of the Frame Sync output pulses.
When not in Burst mode, the Clock unit n operates in continuous mode when enabled, with periodic
Frame Sync pulses and Data samples.
In Burst mode, a single Data transfer starts at each Frame Sync pulse; these pulses are 1-bit wide and
occur only when a Data transfer is requested. Note that the compact stereo modes (16C and 8C) are not
supported in the Burst mode.
SAM D5x/E5x Family Data Sheet
I2S - Inter-IC Sound Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1910