Datasheet

• Clock Unit x Enable bits in the Control A register (CTRLA.CKENx). SYNCBUSY.CKENx is set to '1'
while synchronization is in progress.
• Serializer Enable bits in the Control A register (CTRLA.TXEN and CTRLA.RXEN).
SYNCBUSY.TXEN/RXEN is set to '1' while synchronization is in progress.
The following registers require synchronization when read or written:
• Transmit Data register (TXDATA) is Write-Synchronized. SYNCBUSY.TXDATA is set to '1' while
synchronization is in progress.
• Receive Data register (RXDATA) is Read-Synchronized. SYNCBUSY.RXDATA is set to '1' while
synchronization is in progress.
Synchronization is denoted by the Read-Synchronized or Write-Synchronized property in the register
description.
51.6.11 Loop-Back Mode
For debugging purposes, the I
2
S can be configured to loop back the Transmitter to the Receiver. Writing a
'1' to the Loop-Back Test Mode bit in the Rx Serializer Control register (RXCTRL.RXLOOP)will connect
SDO to SDI, so that transmitted data is also received.
Writing RXCTRL.RXLOOP=0 will restore the normal behavior and connection between Receive Serializer
and SDI pin input. As for other changes to the Serializers configuration, the Receive Serializer must be
disabled before writing the TXCTRL register to update TXCTRL.RXLOOP.
51.7 I
2
S Application Examples
The I
2
S can support several serial communication modes used in audio or high-speed serial links. Some
standard applications are shown in the following figures.
Note: The following examples are not a complete list of serial link applications supported by the I
2
S.
Figure 51-7. Audio Application Block Diagram
Serial Clock
Word Select
Serial Data Out
MSB
Left Channel
LSB MSB
Right Channel
Serial Data Out
Word Select
Serial Clock
I
2
S
SCKn
FSn
SDOm
EXTERNAL
I
2
S
RECEIVER
SAM D5x/E5x Family Data Sheet
I2S - Inter-IC Sound Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1902