Datasheet

51.6.8.2 Interrupts
The I
2
S has the following interrupt sources:
• Receive Ready (RXRDYm): This is an asynchronous interrupt and can be used to wake-up the
device from any sleep mode.
• Receive Overrun (RXORm): This is an asynchronous interrupt and can be used to wake-up the
device from any sleep mode.
• Transmit Ready (TXRDYm): This is an asynchronous interrupt and can be used to wake-up the
device from any sleep mode.
• Transmit Underrun (TXURm): This is an asynchronous interrupt and can be used to wake-up the
device from any sleep mode.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status
and Clear (INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be
individually enabled by writing a one to the corresponding bit in the Interrupt Enable Set (INTENSET)
register, and disabled by writing a one to the corresponding bit in the Interrupt Enable Clear (INTENCLR)
register. An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is
enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or
the I
2
S is reset. Refer to the INTFLAG register for details on how to clear interrupt flags. All interrupt
requests from the peripheral are ORed together on system level to generate one combined interrupt
request to the NVIC. Refer to the “Nested Vector Interrupt Controller” for details. The user must read the
INTFLAG register to determine which interrupt condition is present.
Note: Interrupts must be globally enabled for interrupt requests to be generated. Refer to Nested Vector
Interrupt Controller for details.
Related Links
10.2 Nested Vector Interrupt Controller
51.6.8.3 Events
Not applicable.
51.6.9 Sleep Mode Operation
The I
2
S continues to operate in all sleep modes that still provide its clocks.
51.6.10 Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers
need to be synchronized when written or read.
When executing an operation that requires synchronization, the corresponding Synchronization Busy bit
in the Synchronization Busy register (SYNCBUSY) will be set immediately, and cleared when
synchronization is complete.
If an operation that requires synchronization is executed while the corresponding SYNCBUSY bit is '1', a
peripheral bus error is generated.
The following bits are synchronized when written:
• Software Reset bit in the Control A register (CTRLA.SWRST). SYNCBUSY.SWRST is set to '1' while
synchronization is in progress.
• Enable bit in the Control A register (CTRLA.ENABLE). SYNCBUSY.ENABLE is set to '1' while
synchronization is in progress.
SAM D5x/E5x Family Data Sheet
I2S - Inter-IC Sound Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1901