Datasheet

To configure PDM2 mode, set SLOTSIZE = 0x01 (16-bits), NBSLOTS = 0x00 (1 slots) and
RXCTRL.DATASIZE = 0x00 (32-bit).
51.6.7 Data Formatting Unit
To allow more flexibility, data words received by the Receive Serializer will be formatted by the Receive
Formatting Unit before being stored into the Data Holding register (DATAm). The data words written into
DATAm register will be formatted by the Transmit Formatting Unit before transmission by the Transmit
Serializer .
The formatting options are defined in RXCTRL and TXCTRL:
• SLOTADJ for left or right justification in the slot
• BITREV for bit reversal
• WORDADJ for left or right justification in the data word
• EXTEND for extension to the word size
51.6.8 DMA, Interrupts and Events
Table 51-2. Module Request for I
2
S
Condition DMA
request
DMA request is cleared Interrupt
request
Event input/
output
Receive Ready YES When data is read YES
Transmit Ready (Buffer
empty)
YES When data is written YES
Receive Overrun YES
Transmit Underrun YES
51.6.8.1 DMA Operation
Each Serializer can be connected either to one single DMAC channel or to one DMAC channel per data
slot in Stereo mode. This is selected by writing the RXCTRL/TXCTRL.DMA bit.
Table 51-3. I
2
C DMA Request Generation
SERCTRLm.DMA Mode Slot Parity DMA Request Trigger
0 Receiver all I2S_DMAC_ID_RX_m
Transmitter all I2S_DMAC_ID_TX_m
1 Receiver even I2S_DMAC_ID_RX_m
odd I2S_DMAC_ID_TX_m
Transmitter even I2S_DMAC_ID_TX_m
odd I2S_DMAC_ID_RX_m
The DMAC reads from the RXDATA register and writes to the TXDATA register for all data slots,
successively.
The DMAC transfers may use 32-bit, 16-bit, or or 8-bit transactions according to the value of the
TXCTRL/RXCTRL.DATASIZE field. 8-bit compact stereo uses 16-bit and 16-bit compact stereo uses 32-
bit transactions.
SAM D5x/E5x Family Data Sheet
I2S - Inter-IC Sound Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1900