Datasheet

15.8.9 APBB Mask
Name: APBBMASK
Offset: 0x18
Reset: 0x00018056
Property: PAC Write-Protection
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
RAMECC
Access
R/W
Reset 1
Bit 15 14 13 12 11 10 9 8
TCn3 TCn2 TCCn1 TCCn0 SERCOM3 SERCOM2
Access
R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
EVSYS PORT NVMCTRL DSU USB
Access
R/W R/W R/W R/W R/W
Reset 0 1 1 1 0
Bit 16 – RAMECC RAMECC APBB Clock Enable
Value Description
0
The APBB clock for the RAMECC is stopped.
1
The APBB clock for the RAMECC is enabled.
Bits 13, 14 – TCn TCn APBB Clock Enable
Value Description
0
The APBB clock for the TCn is stopped.
1
The APBB clock for the TCn is enabled.
Bits 11, 12 – TCCn TCCn APBB Clock Enable
Value Description
0
The APBB clock for the TCCn is stopped.
1
The APBB clock for the TCCn is enabled.
Bits 9, 10 – SERCOM SERCOMn APBB Clock Enable
Value Description
0
The APBB clock for the SERCOMn is stopped.
1
The APBB clock for the SERCOMn is enabled.
Bit 7 – EVSYS EVSYS APBB Clock Enable
SAM D5x/E5x Family Data Sheet
MCLK – Main Clock
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 190