Datasheet


MCKn
=
8  SLOTSIZE+1  NBSLOTS+1  MCKDIV+1
MCKOUTDIV+1
If a Master Clock output is not required, the GCLK_I2S generic clock can be configured as SCKn by
writing a '0'to CLKCTRLn.MCKDIV. Alternatively, if the frequency of the generic clock is a multiple of the
required SCKn frequency, the MCKn-to-SCKn divider can be used with the ratio defined by writing the
CLKCTRLn.MCKDIV field.
The FSn pin is used as Word Select in I
2
S format and as Frame Synchronization in TDM format, as
described in 51.6.4 I2S Format - Reception and Transmission Sequence with Word Select and 51.6.5
TDM Format - Reception and Transmission Sequence, respectively.
51.6.2.2 Data Holding Registers
For both the Transmit and the Receive Serializer, the I
2
S user interface includes a Data register (TXDATA
and RXDATA, respectively). They are used to access data samples for all data slots.
51.6.2.2.1 Data Reception Mode
In receiver mode, the RXDATA register stores the received data.
When a new data word is available in the RXDATA register, the Receive Ready bit (RXRDYm) in the
Interrupt Flag Status and Clear register (INTFLAG) is set. Reading the RXDATA register will clear this bit.
A receive overrun condition occurs if a new data word becomes available before the previous data word
has been read from the RXDATA register. Then, the Receive Overrun bit in INTFLAG will be set
(INTFLAG.RXORm). This interrupt can be cleared by writing a '1' to it.
51.6.2.2.2 Data Transmission Mode
In Transmitter mode, the TXDATA register contains the data to be transmitted.
when TXDATA is empty, the Transmit Ready bit in the Interrupt Flag Status and Clear register is set
(INTFLAG.TXRDYm). Writing to TXDATA will clear this bit.
A transmit underrun condition occurs if data present in TXDATA is sent and no new data is written to
TXDATA register before the next time slot. Then, the Transmit Underrun bit in INTFLAG will be set
(INTFLAG.TXURm). This interrupt can be cleared by writing a '1' to it. The Transmit Data when Underrun
bit in the Tx Serializer Control register (TXCTRL.TXSAME) configures whether a zero data word is
transmitted in case of underrun (TXCTRL.TXSAME=0), or the previous data word for the current transmit
slot number is transmitted again (TXCTRL.TXSAME=1).
51.6.3 Master, Controller, and Slave Modes
In Master and Controller modes, the I
2
S provides the Serial Clock, a Word Select/Frame Sync signal and
optionally a Master Clock.
In Controller mode, the I
2
S Serializers are disabled. Only the clocks are enabled and output for external
receivers and/or transmitters.
In Slave mode, the I
2
S receives the Serial Clock and the Word Select/Frame Sync Signal from an
external master. SCKn and FSn pins are inputs.
51.6.4 I
2
S Format - Reception and Transmission Sequence with Word Select
As specified in the I
2
S protocol, data bits are left-adjusted in the Word Select slot, with the MSB
transmitted first, starting one clock period after the transition on the Word Select line.
SAM D5x/E5x Family Data Sheet
I2S - Inter-IC Sound Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1897