Datasheet

51.6.2.1.2 Master Mode and Controller Mode
In Master Mode, the Master Clock (MCKn), the Serial Clock (SCKn), and the Frame Sync Clock (FSn) are
generated by the I
2
S controller. The user can configure the Master Clock, Serial Clock, and Word Select
Frame Sync signal (Word Select in I
2
S mode and Frame Sync in TDM mode) using the Clock Unit n
Control register (CLKCTRLn). MCKn, SCKn, and FSn pins are outputs and a generic clock is used to
derive the I
2
S clocks.
In some applications, audio CODECs connected to the I
2
S pins may require a Master Clock signal with a
frequency multiple of the audio sample frequency fs, such as 256×fs.
In Controller mode, only the Clock generation unit needs to be configured by writing to the CTRLA and
CLKCTRLn registers, where parameters such as clock division factors, Number of slots, Slot size, Frame
Sync signal, clock enable are selected.
51.6.2.1.3 MCKn Clock Frequency
When the I
2
S is in Master mode, writing a '1' to CLKCTRLn.MCKEN will output GCLK_I2S_n as Master
Clock to the MCKn pin. The Master Clock to MCKn pin can be divided by writing to CLKCTRLn.MCKSEL
and CLKCTRLn.MCKOUTDIV. The Master Clock (MCKn) frequency is GCLK_I2S_n frequency divided by
(MCLKOUTDIV+1).
 MCKn =
 GCLK_2_
MCKOUTDIV+1
51.6.2.1.4 SCKn Clock Frequency
When the Serial Clock (SCKn) is generated from GCLK_I2S_n and both CLKCTRLn.MCKSEL and
CLKCTRLn.SCKSEL are zero, the Serial Clock (SCKn) frequency is GCLK_I2S_n frequency divided by
(MCKDIV+1).
i.e.
 CKn =
 GCLK_2_
MCKDIV+1
51.6.2.1.5 Relation Between MCKn, SCKn, and Sampling Frequency fs
Based on sampling frequency fs, the SCKn frequency requirement can be calculated:
• SCKn frequency:

SCKn
=  × total_number_of_bits_per_frame
,
• Where total_number_of_bits_per_frame = number_of_slots × number_of_bits_per_slots.
• The number of slots is selected by writing to the Number of Slots in Frame bit field in the Clock Unit n
Control (CLKCTRLn) register: number_of_slots = NBSLOTS + 1.
• The number of bits per slot (8, 16, 24, or 32 bit) is selected by writing to the Slot Size bit field in
CLKCTRLn: .
• Consequently,

SCKn
= 8 ×  × NBSLOTS + 1 × SLOTSIZE + 1
.
The clock frequencies 
SCKn
and 
MCKn
are derived from the generic clock frequency 
GCLK_I2S_n
:
•

GCLK_I2S_n
= 
SCKn
× CLKCTRLn.MCKDIV + 1
= 8 ×  × NBSLOTS + 1 × SLOTSIZE + 1 × MCKDIV + 1
, and
•

GCLK_I2S_n
= 
MCKn
× MCKOUTDIV + 1
.
Substituting the right hand sides of the two last equations yields:

MCKn
=

GCLK_I2S_n
MCKOUTDIV+1
SAM D5x/E5x Family Data Sheet
I2S - Inter-IC Sound Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1896