Datasheet

Once the configuration has been written, the I
2
S Clock Units and Serializers can be enabled by writing a
'1' to the CKENn, TXEN, and/or RXEN bits and to the ENABLE bit in the Control register (CTRLA). The
Clock Unit n can be enabled alone, in Controller Mode, to output clocks to the MCKn, SCKn, and FSn
pins. The Clock Units must be enabled if Serializers are enabled.
The Clock Units, the Transmit Serializer and the Receive Serializer can be disabled independently by
writing a '0' to CTRLA.CKENn, CTRLA.TXEN, and CTRLA.RXEN, respectively. Once requested to stop,
they will only stop when the pending transmit frames will be completed, if any. When requested to stop,
the ongoing reception of the current slot will be completed and then the Serializer will be stopped.
Example 51-1. Example Requirements: fs=48kHz, MCKn=384×fs
If a 384×fs MCKn Master Clock is required (i.e. 18.432MHz), the I
2
S generic clock could
run at 18.432MHz with a Master Clock Output Division Factor of 1 (selected by writing
CLKCTRLn.MCKOUTDIV=0x0) in order to obtain the desired MCKn frequency.
When using 6 slots per frame (CLKCTRLn.NBSLOTS=0x5) and 32-bit slots
(CLKCTRLn.SLOTSIZE=0x3), the desired SCKn frequency is
f
SCKn
= 48kHz × 6 × 32 = 9.216MHz
This frequency can be achieved by dividing the I
2
S generic clock output of 18.432MHz by
factor 2: Writing CLKCTRLn.MCKDIV=0x1 will select the correct division factor and
output the desired SCKn frequency of 9.216MHz to the SCKn pin.
If MCKn is not required, the generic clock could be set to 9.216MHz and
CLKCTRLn.MCKDIV=0x0.
51.6.2 Basic Operation
The Receiver can be operated by reading the Receive Data Holding register (RXDATA), whenever the
Receive Ready m bit in the Interrupt Flag Status and Clear register (INTFLAG.RXRDYm) is set.
Successive values read from the RXDATA register will correspond to the samples from the left and right
audio channels. In TDM mode, the successive values read from RXDATA correspond to the first slot to
the last slot. For instance, if I
2
S is configured in TDM mode with 4 slots in a frame, then successive
values written to RXDATA register correspond to first, second, third, and fourth slot. The number of slots
in TDM is configured in CLKCTRLn.NBSLOTS.
The Transmitter can be operated by writing to the Transmit Data Holding register (TXDATA), whenever
the Transmit Ready m bit in the Interrupt Flag Status and Clear register (INTFLAG.TXRDYm) is set.
Successive values written to TXDATA register should correspond to the samples from the left and right
audio channels. In TDM mode, the successive values written to TXDATA correspond to the first, second,
third, slot to the last slot. The number of slots in TDM is configured in CLKCTRLn.NBSLOTS.
The Receive Ready and Transmit Ready bits can be polled by reading the INTFLAG register.
The processor load can be reduced by enabling interrupt-driven operation. The RXRDYm and/or
TXRDYm interrupt requests can be enabled by writing a '1' to the corresponding bit in the Interrupt
Enable register (INTENSET). The interrupt service routine associated to the I
2
S interrupt request will then
be executed whenever Receive Ready or Transmit Ready status bits are set.
The processor load can be reduced further by enabling DMA-driven operation. Then, the DMA channels
support up to four trigger sources from the I
2
S peripheral. These four trigger sources in DMAC channel
are
• I2S RX 0,
SAM D5x/E5x Family Data Sheet
I2S - Inter-IC Sound Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1894