Datasheet

22. DMAC – Direct Memory Access Controller
51.5.5 Interrupts
The interrupt request line is connected to the interrupt controller. Using I
2
S interrupts requires the
interrupt controller to be configured first.
Related Links
10.2 Nested Vector Interrupt Controller
51.5.6 Events
Not applicable.
51.5.7 Debug Operation
When the CPU is halted in Debug mode, this peripheral will continue normal operation. If the peripheral is
configured to require periodical service by the CPU through interrupts or similar, improper operation or
data loss may result during debugging. This peripheral can be forced to halt operation during debugging.
51.5.8 Register Access Protection
Registers with write access can be optionally write-protected by the Peripheral Access Controller (PAC),
except for the following:
• DATAm
• INTFLAG
• SYNCBUSY
Note: Optional write protection is indicated by the "PAC Write Protection" property in the register
description.
Write protection does not apply for accesses through an external debugger.
51.5.9 Analog Connections
Not applicable.
51.6 Functional Description
51.6.1 Principle of Operation
The I
2
S uses three or four communication lines for synchronous data transfer:
• SDO output for Transmit Serializer
• SDI input for Receive Serializer
• SCKn for the serial clock in Clock Unit n (n=0..1)
• FSn for the frame synchronization or I
2
S word select, identifying the beginning of each frame
• Optionally, MCKn to output an oversampling clock to an external codec
I
2
S data transfer is frame based, where a serial frame:
• Starts with the frame synchronization active edge, and
• Consists of 1 to 8 data slots, that are 8-, 16-, 24-, or 32-bit wide.
Each data slot is used to transfer one data sample of 8, 16, 18, 20, 24 or 32 bits.
Frame based data transfer is described in the following figure:
SAM D5x/E5x Family Data Sheet
I2S - Inter-IC Sound Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1891