Datasheet

Table Of Contents
...........continued
Pin Name Pin Description Type
SDO Serial Data Output for Transmit Serializer Output
SDI Serial Data Input for Receive Serializer Input
Note:  One signal can be mapped on several pins.
Related Links
6. I/O Multiplexing and Considerations
51.5 Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described below.
51.5.1 I/O Lines
Using the I
2
S I/O lines requires the I/O pins to be configured.
The I
2
S pins may be multiplexed with I/O Controller lines. The user must first program the I/O Controller
to assign the desired I
2
S pins to their peripheral function. If the I
2
S I/O lines are not used by the
application, they can be used for other purposes by the I/O Controller. It is required to enable only the I
2
S
inputs and outputs actually in use.
Related Links
32. PORT - I/O Pin Controller
51.5.2 Power Management
The I
2
S will continue to operate in any sleep mode where the selected source clocks are running.
51.5.3 Clocks
The clock for the I
2
S bus interface (CLK_I2S_APB) is generated by the Power Manager. This clock is
disabled at reset, and can be enabled in the Power Manager. It is recommended to disable the I
2
S before
disabling the clock, to avoid freezing the I
2
S in an undefined state.
There are two generic clocks, GCLK_I2S_0 and GCLK_I2S_1, connected to the I
2
S peripheral, one for
each I
2
S clock unit. The generic clocks (GCLK_I2S_n, n=0..1) can be set to a wide range of frequencies
and clock sources. The GCLK_I2S_n must be enabled and configured before use.
The GCLK_I2S_n clocks must be enabled and configured before triggering Software Reset, so that the
logic in all clock domains can be reset.
The generic clocks are only used in Master mode and Controller mode. In Master mode, the clock from
clock unit 0 can be used for both Serializers to handle synchronous transfers, or a separate clock from
different clock units can be used for each Serializer to handle transfers on non-related clocks.
Related Links
14. GCLK - Generic Clock Controller
51.5.4 DMA
The DMA request lines are connected to the DMA Controller (DMAC). Using the I
2
S DMA requests
requires the DMA Controller to be configured first.
Related Links
SAM D5x/E5x Family Data Sheet
I2S - Inter-IC Sound Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1890