Datasheet

• Master, slave, and controller modes:
– Master: Data received/transmitted based on internally-generated clocks. Output Serial Clock on
SCKn pin, Master Clock on MCKn pin, and Frame Sync Clock on FSn pin
– Slave: Data received/transmitted based on external clocks on Serial Clock pin (SCKn) or Master
Clock pin (MCKn)
– Controller: Only output internally generated Master clock (MCKn), Serial Clock (SCKn), and
Frame Sync Clock (FSn)
• Individual enabling and disabling of Clock Units and Serializers
• DMA interfaces for each Serializer receiver or transmitter to reduce processor overhead:
– Either one DMA channel for all data slots or
– One DMA channel per data channel in stereo
• Smart Data Holding register management to avoid data slots mix after overrun or underrun
51.3 Block Diagram
Figure 51-1. I
2
S Block Diagram
Serializers
Power
Manager
Peripheral Bus
Bridge
DMA
Controller
Interrupt
Controller
2 Clock Units
Peripheral Bus Interface
PORT
IRQ
Tx
Rx
APB
APB clock
CLK_I2S_APB
2 Generic clocks
GCLK_I2S_0
GCLK_I2S_1
I
2
S
MCKn
SCKn
FSn
Transmit Serializer
and
Receive Serializer
SDO
SDI
51.4 Signal Description
Table 51-1.
Pin Name Pin Description Type
MCKn Master Clock for Clock Unit n Input/Output
SCKn Serial Clock for Clock Unit n Input/Output
FSn I
2
S Word Select or TDM Frame Sync for Clock Unit n Input/Output
SAM D5x/E5x Family Data Sheet
I2S - Inter-IC Sound Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1889