Datasheet

15.8.8 APBA Mask
Name: APBAMASK
Offset: 0x14
Reset: 0x000007FF
Property: PAC Write-Protection
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
TCn1 TCn0 SERCOM1 SERCOM0 FREQM EIC RTC WDT
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 1 1 1
Bit 7 6 5 4 3 2 1 0
GCLK SUPC OSC32KCTRL OSCCTRL RSTC MCLK PM PAC
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1
Bits 14, 15 – TCn TCn APBA Clock Enable
Value Description
0
The APBA clock for the TCn is stopped.
1
The APBA clock for the TCn is enabled.
Bits 12, 13 – SERCOM SERCOMn APBA Clock Enable
Value Description
0
The APBA clock for the SERCOMn is stopped.
1
The APBA clock for the SERCOMn is enabled.
Bit 11 – FREQM FREQM APBA Clock Enable
Value Description
0
The APBA clock for the FREQM is stopped.
1
The APBA clock for the FREQM is enabled.
Bit 10 – EIC EIC APBA Clock Enable
Value Description
0
The APBA clock for the EIC is stopped.
1
The APBA clock for the EIC is enabled.
Bit 9 – RTC RTC APBA Clock Enable
SAM D5x/E5x Family Data Sheet
MCLK – Main Clock
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 188