Datasheet

Value Description
0
The AHB clock for the ICM is stopped.
1
The AHB clock for the ICM is enabled.
Bits 17, 18 – CANn CANn AHB Clock Enable
Value Description
0
The AHB clock for the CANn is stopped.
1
The AHB clock for the CANn is enabled.
Bits 15, 16 – SDHCn SDHCn AHB Clock Enable
Value Description
0
The AHB clock for the SDHCn is stopped.
1
The AHB clock for the SDHCn is enabled.
Bit 14 – GMAC GMAC AHB Clock Enable
Value Description
0
The AHB clock for the GMAC is stopped.
1
The AHB clock for the GMAC is enabled.
Bit 13 – QSPI QSPI AHB Clock Enable
Value Description
0
The AHB clock for the QSPI is stopped.
1
The AHB clock for the QSPI is enabled.
Bit 12 – PAC PAC AHB Clock Enable
Value Description
0
The AHB clock for the PAC is stopped.
1
The AHB clock for the PAC is enabled.
Bits 11,7,5 – Reserved Reserved bits
Reserved bits are unused and reserved for future use. For compatibility with future devices, always write
reserved bits to their reset value. If no reset value is given, write 0.
Bit 10 – USB USB AHB Clock Enable
Value Description
0
The AHB clock for the USB is stopped.
1
The AHB clock for the USB is enabled.
Bit 9 – DMAC DMAC AHB Clock Enable
Value Description
0
The AHB clock for the DMAC is stopped.
1
The AHB clock for the DMAC is enabled.
Bit 8 – CMCC CMCC AHB Clock Enable
Value Description
0
The AHB clock for the CMCC is stopped.
1
The AHB clock for the CMCC is enabled.
Bit 6 – NVMCTRL NVMCTRL AHB Clock Enable
SAM D5x/E5x Family Data Sheet
MCLK – Main Clock
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 186