Datasheet

Value Description
0
The Lock Update bit in the Control B register (CTRLB.LUPD) is not affected by overflow/
underflow, and re-trigger events
1
CTRLB.LUPD is set to '1' on each overflow/underflow or re-trigger event.
Bits 13:12 – PRESCYNC[1:0] Prescaler and Counter Synchronization
These bits select if on re-trigger event, the Counter is cleared or reloaded on either the next GCLK_TCCx
clock, or on the next prescaled GCLK_TCCx clock. It is also possible to reset the prescaler on re-trigger
event.
These bits are not synchronized.
Value Name Description
Counter Reloaded Prescaler
0x0 GCLK Reload or reset Counter on next
GCLK
-
0x1 PRESC Reload or reset Counter on next
prescaler clock
-
0x2 RESYNC Reload or reset Counter on next
GCLK
Reset prescaler counter
0x3 Reserved
Bit 11 – RUNSTDBY Run in Standby
This bit is used to keep the TCC running in Standby mode.
This bit is not synchronized.
Value Description
0
The TCC is halted in standby.
1
The TCC continues to run in standby.
Bits 10:8 – PRESCALER[2:0] Prescaler
These bits select the Counter prescaler factor.
These bits are not synchronized.
Value Name Description
0x0
DIV1 Prescaler: GCLK_TCC
0x1
DIV2 Prescaler: GCLK_TCC/2
0x2
DIV4 Prescaler: GCLK_TCC/4
0x3
DIV8 Prescaler: GCLK_TCC/8
0x4
DIV16 Prescaler: GCLK_TCC/16
0x5
DIV64 Prescaler: GCLK_TCC/64
0x6
DIV256 Prescaler: GCLK_TCC/256
0x7
DIV1024 Prescaler: GCLK_TCC/1024
Bits 6:5 – RESOLUTION[1:0] Dithering Resolution
These bits increase the TCC resolution by enabling the dithering options.
These bits are not synchronized.
SAM D5x/E5x Family Data Sheet
TCC – Timer/Counter for Control Applications
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1843