Datasheet

Table Of Contents

Figure 49-36. Dead-Time Generator Timing Diagram

"dti_cnt"

"OTMX output"

"DTLS"

"DTHS"

DTILS

DTIHS

The pattern generator unit produces a synchronized bit pattern across the port pins it is connected to.

The pattern generation features are primarily intended for handling the commutation sequence in

brushless DC motors (BLDC), stepper motors, and full bridge control. See also Figure 49-37.

Figure 49-37. Pattern Generator Block Diagram

COUNT

UPDATE

BV BVPGEB[7:0]

PGE[7:0]

PGVB[7:0]

PGV[7:0]

SWAP output

ENEN

WOx[7:0]

As with other double-buffered timer/counter registers, the register update is synchronized to the UPDATE

condition set by the timer/counter waveform generation operation. If synchronization is not required by

the application, the software can simply access directly the PATT.PGE, PATT.PGV bits registers.

49.6.4 Master/Slave Operation

Two or more TCC instances sharing the same GCLK_TCC clock, can be linked to provide more

synchronized CC channels. The operation is enabled by setting the Master Synchronization bit in Control

A register (CTRLA.MSYNC) in the Slave instance. When the bit is set, the slave TCC instance will

synchronize the CC channels to the Master counter.