Datasheet

In Normal and Match Frequency, the WAVE.POLx value represents the initial state of the waveform
output.
49.6.2.6 Double Buffering
The Pattern (PATT), Period (PER) and Compare Channels (CCx) registers are all double buffered. Each
buffer register has a buffer valid (PATTBUFV, PERBUFV and CCBUFVx) bit in the STATUS register,
which indicates that the Buffer register contains a valid value that can be copied into the corresponding
register. As long as the respective Buffer Valid Status flag (PATTBUFV, PERBUFV or CCBUFVx) are set
to '1', the related SYNCBUSY bits are set (SYNCBUSY.PATT, SYNCBUSY.PER or SYNCBUSY.CCx), a
write to the respective PATT/PATTBUF, PER/PERBUF or CCx/CCBUFx registers will generate a PAC
error, and read access to the respective PATT, PER or CCx register is invalid.
When the Buffer Valid Flag bit in the STATUS register is '1' and the Lock Update bit in the CTRLB register
is set to '0', (writing CTRLBCLR.LUPD to '1'), double buffering is enabled: the data from buffer registers
will be copied into the corresponding register under hardware UPDATE conditions, then the Buffer Valid
flags bit in the STATUS register are automatically cleared by hardware.
Note: Software update command (CTRLBSET.CMD=0x3) act independently of LUPD value.
A compare register is double buffered as in the following figure.
Figure 49-9. Compare Channel Double Buffering
=
EN
EN
"APB write enable"
"data write"
UPDATE
COUNT
"match"
CCBUFx
CCx
BV
Both the registers (PATT/PER/CCx) and corresponding Buffer registers (PATTBUFPERBUF/CCBUFx) are
available in the I/O register map, and the double buffering feature is not mandatory. The double buffering
is disabled by writing a '1' to CTRLSET.LUPD.
Note: In NFRQ, MFRQ or PWM Down-Counting Counter mode (CTRLBSET.DIR=1), when double
buffering is enabled (CTRLBCLR.LUPD=1), PERBUF register is continuously copied into the PER
independently of update conditions.
Changing the Period
The counter period can be changed by writing a new Top value to the Period register (PER or CC0,
depending on the Waveform Generation mode), any period update on registers (PER or CCx) is effective
after the synchronization delay, whatever double buffering enabling is.
SAM D5x/E5x Family Data Sheet
TCC – Timer/Counter for Control Applications
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1813