Datasheet

Table Of Contents
Recoverable faults and non-recoverable faults
Output matrix
Dead-time insertion
Swap
Pattern generation
See also Figure 49-1.
The output matrix (OTMX) can distribute and route out the TCC waveform outputs across the port pins in
different configurations, each optimized for different application types. The Dead-Time Insertion (DTI) unit
splits the four lower OTMX outputs into two non-overlapping signals: the non-inverted Low Side (LS) and
inverted High Side (HS) of the waveform output with optional dead-time insertion between LS and HS
switching. The SWAP unit can swap the LS and HS pin outputs, and can be used for fast decay motor
control.
The pattern generation unit can be used to generate synchronized waveforms with constant logic level on
TCC UPDATE conditions. This is useful for easy stepper motor and full bridge control.
The non-recoverable fault module enables event controlled fault protection by acting directly on the
generated waveforms of the timer/counter compare channel outputs. When a non-recoverable fault
condition is detected, the output waveforms are forced to a preconfigured value that is safe for the
application. This is typically used for instant and predictable shut down and disabling high current or
voltage drives.
The count event sources (TCE0 and TCE1) are shared with the non-recoverable fault extension. The
events can be optionally filtered. If the filter options are not used, the non-recoverable faults provide an
immediate asynchronous action on waveform output, even for cases where the clock is not present. For
further details on how to configure asynchronous events routing, refer to section EVSYS – Event System.
Related Links
31. EVSYS – Event System
49.6.2 Basic Operation
49.6.2.1 Initialization
The following registers are enable-protected, meaning that they can only be written when the TCC is
disabled(CTRLA.ENABLE=0):
Control A (CTRLA) register, except Run Standby (RUNSTDBY), Enable (ENABLE) and Software
Reset (SWRST) bits
Recoverable Fault n Control registers (FCTRLA and FCTRLB)
Waveform Extension Control register (WEXCTRL)
Drive Control register (DRVCTRL)
Event Control register (EVCTRL)
Enable-protected bits in the CTRLA register can be written at the same time as CTRLA.ENABLE is
written to '1', but not at the same time as CTRLA.ENABLE is written to '0'. Enable-protection is denoted
by the “Enable-Protected” property in the register description.
Before the TCC is enabled, it must be configured as outlined by the following steps:
1. Enable the TCC bus clock (CLK_TCCx_APB).
2. If Capture mode is required, enable the channel in Capture mode by writing a '1' to the Capture
Enable bit in the Control A register (CTRLA.CPTEN).
SAM D5x/E5x Family Data Sheet
TCC – Timer/Counter for Control Applications
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1804